1. Technical Field
The present invention relates to a bus control technique which performs a recovery process from a fault in an input and output bus.
2. Related Art
The PCI (Peripheral Component Interconnect) standard has been widely applied as the standard for buses serving as signal transmission paths in computer systems. In known computer systems, in the case where an error not otherwise specified of a transaction (for example, address parity error) in which a fault has occurred in a PCI bus is detected during access from a central processing unit (CPU) in the computer system to PCI devices (input and output devices electrically connected to the PCI bus), or, during access from the PCI devices to a memory in the computer system, a system error signal line becomes active. As described above, when the system error signal line is asserted, an error occurrence is notified to the CPU (or OS: operating system) via a signal line for NMI (Non Mask Interrupt). This notification can make the CPU know the occurrence of the error. However, the CPU cannot specify the source of the aforementioned error occurrence; therefore, an appropriate error process cannot be executed. Therefore, the CPU abnormally aborts the system (brings the system down) at a time of the occurrence of NMI in order to inhibit error propagation.
On the other hand, a fault such as a data parity error which enables to specify a transaction in which a fault has occurred in the PCI bus is reported to the CPU as an error reply. With respect to this fault, an exception handler of the OS performs a special error process.
However, specifications and control methods of PCI devices to be connected are largely different depending on the PCI devices; therefore, the exception handler of the OS cannot perform error processes of all the PCI devices by itself completely. Therefore, in the case where the appropriate error process cannot be performed, the exception handler makes the system abort (brings the system down) abnormally in order to inhibit the propagation of the aforementioned error.
A related art capable of avoiding abnormal stop of the system as described above is disclosed in Japanese Laid-open patent publication NO. 2005-215809, for example. A computer system disclosed in Japanese Laid-open patent publication NO. 2005-215809 has a PCI bus controller, a bridge driver (program for PCI bus fault control), and a device driver. The PCI bus controller includes a bus fault indicator (ERI) which lights when an error is detected in a PCI bus. At a time of lighting the bus fault indicator, the PCI bus controller makes the PCI bus transit to a degeneracy state (that is, a use of a part of the PCI bus is stopped). The bridge driver has a function of detecting a fault of the PCI bus by monitoring the degeneracy state of the PCI bus controller (PBC) and notifying a fault occurrence to a corresponding device driver at a time of the occurrence of an error of the PCI bus. Furthermore, the bridge driver has a function of issuing instruction which is for recovering the PCI bus to the PCI bus controller, and then notifying the device driver that the recovery has been completed. When the device driver receives recovery completion notification, the device driver executes an initial setting process for the PCI device and incorporates the PCI device in the computer system again.
In the technique as disclosed in Japanese Laid-open patent publication NO. 2005-215809, the fault of the PCI bus is not notified to the exception handler of the CPU and OS; the bridge driver and the device driver work together to detect the fault of the PCI bus without occurrence of the system down, and perform the recovery.